Semiconductor memory device

ABSTRACT

A semiconductor memory device for error correction encoding and decoding able to avoid erroneous judgment occurring due to erroneous correction when a nonvolatile memory is in a predetermined initial state, wherein, at the time of writing, write data and predetermined status data, for example, erasure data when the nonvolatile memory is in an erasure state are compared and, when the result of the comparison is that the write data coincides with the erasure data, the erasure data is selected and, conversely when they do not coincide, the encoded data obtained by error correction encoding the write data is selected and written into the nonvolatile memory, while at the time of reading, when the result of the comparison between the read data and the erasure data from the nonvolatile memory is that the read data coincides with the erasure data, the erasure data is selected and, conversely when they do not coincide, the decoded data obtained by error correction decoding the read data is selected and output.

BACKGROUND OF THE INVENTION

[0001] 1. Field of the Invention

[0002] The present invention relates to a semiconductor memory device,for example, a semiconductor memory device for storing encoded dataobtained by encoding input data for error connection at the time ofwriting in a nonvolatile memory and error correction decoding the dataread from the nonvolatile memory at the time of reading.

[0003] 2. Description of the Related Art

[0004] In a nonvolatile memory device storing data using a nonvolatilememory, to secure reliability of the storage data, error detection anderror correction are carried out at the time of reading. For thisreason, the input data is encoded for the error detection and the errorcorrection before writing it into the nonvolatile memory.

[0005] The encoding system used in the error correction encodingincludes for example Reed Solomon encoding, BCH encoding, etc. Theseerror correction ncoding systems ncode th input data and g nerate rrorcorrection codes. The error correction codes ar then stor d by thnonvolatil m mory. At the time of r ading, the error corr ction ncod ddata is read from th nonvolatile memory. The original data is restoredby decoding corresponding to the error correction encoding based on theread data.

[0006] By the above encoding and decoding, for example, even if an erroroccurs at the time of for example the writing or reading with respect tothe nonvolatile memory, this error is corrected by the decoding, so theinput data can be correctly restored and the reliability of thenonvolatile memory device can be enhanced.

[0007] Summarizing the problem to be solved by the invention, in theencoding and decoding using the above conventional nonvolatile memory,when the data read from the nonvolatile memory after erasure all becomes“1”, the error correction encoding bits are not all “1”. This means thatan error detection/correction circuit for performing the error detectionand the error correction outputs a judgment result “there is error” whenreading data from the nonvolatile memory finished being erased.

[0008] Further, when the data is written as all “1” at the time ofwriting, the encoding bits for the error detection/error correction arenot “1”, therefore, even bits which originally should not be writtenhave to be written by making the error correction encoding bits “0”.Namely, when the nonvolatile memory is in a certain sp cific initialstate, for example, an rasur state, all memory cells of the nonvolatilememory are held at a constant state, so all of the storage data of thenonvolatile memory becomes a constant value, for example “1”. In thiscase, when error correction decoding data read from the nonvolatilememory, a judgment result that there is an error is obtained, so thereis the disadvantage that the original state of the data stored in thenonvolatile memory can no longer be correctly represented.

SUMMARY OF THE INVENTION

[0009] An object of the present invention is to provide a semiconductormemory device for error correction encoding and decoding write and readdata of a nonvolatile memory and able to avoid erroneous judgmentoccurring due to the error detection when the nonvolatile memory is in apredetermined initial state.

[0010] To attain the above object, according to a first aspect of thepresent invention, there is provided a semiconductor memory devicecomprising an encoding means for encoding input data according to apredetermined error correction encoding system; a comparing means forcomparing the input data and a predetermined status data; a sel ctingmeans for s lecting either of the input data or encoded data output fromthe encoding means in accordance with a comparison result of thecomparing means; and a nonvolatile memory for storing data selected bythe selecting means, wherein the nonvolatile memory holds the statusdata in a predetermined initialization state.

[0011] Preferably, the nonvolatile memory holds the status data in theerasure state.

[0012] Preferably, the selecting means selects the status data when theinput data coincides with the status data and selects the encoded dataoutput from the encoding means when the input data does not coincidewith the status data.

[0013] According to a second aspect of the invention, there is provideda semiconductor memory device comprising a decoding means for decodingdata read from a nonvolatile memory according to a predetermined errorcorrection decoding system; a comparing means for comparing data inputto the decoding means and predetermined status data; and a selectingmeans for selecting either of the status data or decoded data outputfrom the decoding means in accordance with a comparison result of thecomparing means, wherein the nonvolatile memory holds the status data ina predet rmined initialization state.

[0014] Pr f rably, th selecting means selects th status data wh n thread data coincides with th status data and s lects the decoded datawhen th read data does not coincide with the status data.

[0015] According to a third aspect of the present invention, there isprovided a semiconductor memory device for error correctionencoding/decoding input/output data, comprising an encoding means forencoding input data according to a predetermined error correctionencoding system; a comparing means for comparing the input data andpredetermined status data; a first selecting means for selecting eitherof the input data or encoded data output from the encoding means inaccordance with a comparison result of the comparing means; anonvolatile memory for storing data selected by the selecting means; adecoding means for decoding data read from the nonvolatile memoryaccording to a predetermined error correction decoding system; acomparing means for comparing the decoded data output by the decodingmeans and the status data; and a second selecting means for selectingeither of the status data or the decoded data in accordance with thecomparison result of the comparing means, wherein the nonvolatile memoryholds the status data in a predetermined initialization state.

[0016] According to the present invention, at the time of writing, writedata and predetermined status data, for exampl rasur data at the time ofthe erasur state of the nonvolatil m mory, ar compared. In accordancwith the result of the comparison, when the write data coincides withthe erasure data, the erasure data is selected, and conversely when theydo not coincide, the encoded data obtained by error correction encodingthe write data is selected and written into the nonvolatile memory. Atthe time of reading, in accordance with the comparison result betweenthe read data and the erasure data from the nonvolatile memory, when theread data coincides with the erasure data, the erasure data is selected,and conversely when they do not coincide, the decoded data obtained byerror correction decoding the read data is selected and output. By this,occurrence of an erroneous decision of the error correction in writedata completely coinciding with the erasure data is avoided.

BRIEF DESCRIPTION OF THE DRAWINGS

[0017] These and other objects and features of the present inventionwill become clearer from the following description of the preferredembodiments given with reference to the attached drawings, wherein:

[0018]FIG. 1 is a view of the configuration of an embodim nt of asemiconductor memory device according to the present invention;

[0019]FIG. 2 is a circuit diagram of the configuration of an rror corrction circuit;

[0020]FIGS. 3A and 3B are sectional views of an example of theconfiguration of a nonvolatile memory cell;

[0021]FIGS. 4A and 4B are conceptual views of the erase and writeoperation of a NOR type nonvolatile memory;

[0022]FIGS. 5A and 5B are conceptual views of the erase and writeoperation of a NAND type nonvolatile memory;

[0023]FIG. 6 is a flow chart of the operation at the time of writing;

[0024]FIG. 7 is a flow chart of the operation at the time of reading;and

[0025]FIG. 8 is a diagram of an example of write data.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0026] Preferred embodiments of the present invention will be describedin detail below while referring to the attached figures.

[0027]FIG. 1 is a view of the configuration of an embodiment of asemiconductor memory device according to the present invention. Asillustrated, a semiconductor memory device 100 of the present embodimentis configured by a control unit and a memory unit. The memory unit isconfigured by a nonvolatile memory, for example, a so-call d flashmemory (FMRY) 180 erasing data in units of blocks or th chip unit. Acontrol unit 110 is configur d by a partial circuit for realizing anerror det ction/correction function, an interfac for input/output of thedata, and a buffer (register) for temporarily storing the input/outputdata, etc. Note that the semiconductor memory device of the presentembodiment can be used to form a portable type memory device having aninformation storage function using a flash memory, for example, a memorycard. Other than this, it is also possible to form part of for example aso-called IC card for achieving a certain specific function by addingpredetermined processing to memory information other than informationstorage.

[0028] As shown in FIG. 1, in the semiconductor memory device 100 of thepresent embodiment, the control unit 110 is configured by an interfaceunit (I/F) 120, a write register (WREG) 130, a read register (RREG) 140,an error correction circuit (ECC) (ENC/DEC circuit) 150, a page buffer(PGBUF) 160, and a flash memory interface (FM I/F) 170. Below, anexplanation will be given of components of the control unit 110.

[0029] The interface unit 120 holds a control signal CTL and write dataD_(in) input from the outside and outputs the same to other partialcircuits of the control unit 110. Further, the interface unit 120 holdsthe control signal from th control unit 110 and r ad data D_(out) andoutputs the same to th outside.

[0030] Th write register 130 stor s the control data for controlling thewriting and control commands input from the interface unit 120 andoutputs the stored data to th flash memory interface 170 at apredetermined timing. The read register 140 stores the control data andthe control commands etc. output from the flash memory interface 170 andoutputs the same to the interface unit 120 at a predetermined timing.

[0031] The error correction circuit 150 performs the error correctionencoding and decoding. When writing the data into the flash memory 180,the write data D_(in) input from the outside is input via the interfaceunit 120 to the page buffer 160. Then, the write data D_(in) is readfrom the page buffer 160 and input to the error correction circuit 150.The error correction circuit 150 error correction encodes the dataD_(in) based on the encoding system determined in advance and outputsthe encoded encoding code to the flash memory interface 170.

[0032] On the other hand, when reading the storage data from the flashmemory 180, the read data is input via the flash memory interface 170 tothe error correction circuit 150. The error correction circuit 150decodes the read data corresponding to the encoding used in the encodingat the time of writing and detects and corrects the error included inthe r ad data. Then, it inputs the data after correction to the pagebuffer 160.

[0033] The page buffer 160 is provided for holding the write data andthe read data at the time of writing and reading. At the time ofwriting, it stores the write data D_(in) input from the interface unit120 and then outputs the stored data to the error correction circuit 150or the flash memory interface 170 at a predetermined timing. At the timeof reading, the page buffer 160 stores the read data output from theflash memory interface 170 or the data D_(out) after the errorcorrection output from the error correction circuit 150 and outputs thesame to the interface unit 120 at a predetermined timing. By providingthe page buffer 160, the timing of the data input/output can beadjusted.

[0034] Next, an explanation will be given of the configuration andoperation of the error correction circuit 150 in the semiconductormemory device according to the present embodiment. FIG. 2 is a view ofthe configuration of the partial circuit including the error correctioncircuit 150, the flash memory interface 170, and the flash memory 180.

[0035] As shown in FIG. 2, the error correction circuit 150 isconfigured by an rror corr ction encoding circuit (EEC ENC) 20, a slection circuit (SEL) 30, an erasure data regist r (ED REG) 40, acoincidenc detection circuit (COIN DET) 50, a selection circuit (SEL)60, an error correction decoding circuit (ECC DEC) 70, and a RAM 80.Below, an explanation will be given of the components of the errorcorrection circuit 150.

[0036] The ECC encoding circuit 20 error correction encodes the writedata D_(in) of input based on the encoding system determined in advance.The error correction codes encoded by the ECC encoding circuit 20 areoutput to the selection circuit 30.

[0037] The selection circuit 30 selects the error correction code outputfrom the ECC encoding circuit 20 and the erasure data output from theerasure data register 40 in accordance with the detection result of thecoincidence detection circuit 50. The data selected by the selectioncircuit 30 is written into the flash memory 180 via the flash memoryinterface 170.

[0038] The erasure data register 40 stores the storage data of eachmemory cell when the flash memory 180 is in the erasure state(hereinafter, this will be simply referred to as the erasure data D_(E)for convenience) in predetermined units, for example, units of bytes orunits of pluralities of bytes. Then, the erasure data register 40supplies th stored erasure data D_(E) to the coincidence detectioncircuit 50 and the selection circuits 30 and 60.

[0039] The coincid nce det ction circuit 50 compares the erasur dataD_(E) output from the rasure data r gister 40 with the write data D_(in)or the read data D_(R), outputs a comparison signal S_(CP) indicatingthe result of comparison to the selection circuit 30 and the selectioncircuit 60, and controls the selection operation of these selectioncircuits.

[0040] The selection circuit 60 selects either of the erasure dataoutput by the erasure data register 40 or the result of the errorcorrection decoding output by the ECC decoding circuit 70 in accordancewith the comparison signal S_(CP) indicating the detection result of thecoincidence detection circuit 50 and outputs the selected data as theread data D_(out).

[0041] The ECC decoding circuit 70 performs reverse processing to theerror correction encoding in the ECC encoding circuit 20 on the dataD_(R) read from the flash memory 180. Namely, the ECC decoding circuit70 performs the predetermined error correction decoding on the read dataD_(R) to restore the original data.

[0042] The RAM 80 stores the read data D_(R) output from the flashmemory interface 170 and supplies the stored data D_(R) to the ECCdecoding circuit 70 at a predetermined timing. Namely, the RAM 80functions as a buffer for temporarily holding the read data D_(R.) Usingthe RAM 80, the output timing of the read data D_(R) can be adjusted.

[0043] In the present embodiment, the flash memory 180 for storing thewrite data erases the data in predetermined units. For example, theflash memory 180 erases data in units of blocks, in units of pages, orfor the entire chip. After the erasure, the same data is held in allmemory cells of the flash memory 180. The held data at this time is heldin the erasure data register 40 in units of bytes or units ofpluralities of bytes.

[0044]FIGS. 3A and 3B are views of the configuration of an example of amemory cell configuring the flash memory 180. As illustrated, the memorycell of the flash memory has a floating gate 250 formed on the substratesurface of a channel forming region 230 of a MOS transistor betweenimpurity regions 210 and 220 formed on a substrate 200 via a gateinsulating film 240 and further has a gate electrode 270 formed via theinsulating film 260 between upper layers of the surface. Side walls 280are formed on side surfaces of the floating gate 250 and the gateelectrode 270 by an insulator. Note that the floating gate 250 is formedby a conductive material, for example, polysilicon, and the gateelectrode 270 is formed by the conductive material, for example,polysilicon or a metal layer.

[0045] The floating gate of th memory cell having the above constitutionis el ctrically insulated from its surroundings, so charges inject dinto the floating gate are electrically sealed in and almost permanentlyheld. The threshold voltage of the memory cell changes in accordancewith the amount of charges injected into the floating gate, so the datacorresponding to this threshold voltage is stored by the memory cell.For this reason, a nonvolatile data storage able to hold the storagedata even if the supply of the power source is not received can berealized.

[0046]FIG. 3A shows the memory cell in the erasure state, and FIG. 3Bshows the memory cell in the writing state. As illustrated, the erasurestate is the state where positive charges (+) are injected in thefloating gate 250, that is, the state where electrons are drained. Atthis time, the threshold voltage of the memory cell becomes lower thanthe usual voltage. On the other hand, the writing state is the statewhere negative charges (electrons) are injected in the floating gate250. At this time, the threshold voltage of the memory cell becomeshigher than the usual voltage.

[0047] When defining that the data “1” corresponds to a memory cell inthe erasure state and the data “0” corresponds to a memory cell in thewriting state, in the case of th erasure state, on byte's worth of thstorage data of the memory cell becomes “&hFF” in hexadecimal notation.Namely, all bits of one byte ar held at “1”.

[0048] The flash memory 180 is configured by a plurality of memory cellsarranged in a matrix. Gate electrodes of the memory cells of each roware connected to the same word line, and sources or drains of the memorycells of each column are connected to the same bit line. Depending thearrangement of the memory cells, there are the NOR type, NAND type, etc.Below, an explanation will be given of the configurations and operationsof the NOR type and NAND type flash memories.

[0049]FIGS. 4A and 4B are views of the configuration of a NOR type flashmemory and the erase and write operations thereof. FIG. 4A shows theoperation at the time of erasing, and FIG. 4B shows the operation at thetime of writing. As shown in FIGS. 4A and 4B, the NOR type flash memoryhas the memory cells of memory cell columns adjacent to each otherconnected to the same bit line BL.

[0050] As shown in FIG. 4A, at the time of erasing, a positive highvoltage is applied to the substrate. Due to this, the electrons of thefloating gate are drained to the substrate side, so the positive chargeswill accumulated in the floating gate equivalently. For this reason, thethreshold voltage of the memory cell is lowered. Not that, as explainedabove, the storage data of th m mory c ll in the erasure statecorresponds to “1”.

[0051] The erasing of data in the memory cell explained above is carriedout with respect to a plurality of memory cells together. Contrary tothis, the writing of data in a memory cell is carried out with respectto an individual memory cell. When writing, the memory cell connected toboth of the selected word line WL and the selected bit line BL isselected and written in.

[0052] As shown in FIG. 4B, at the time of writing, the source of thememory cell is held at a ground potential GND (0V), and a write voltageV_(PP) is applied to the selected word line WL. The other unselectedword lines are held at the ground potential GND. At this time, the datato be written into the selected memory cell is determined in accordancewith the voltage applied to the selected bit line BL. For example, whena voltage of 0V is applied to the selected bit line (corresponding tothe write data “0”), the electrons are injected into the floating gatefrom the channel region of the selected memory cell connected to theselected bit line BL. For this reason, the threshold voltage of thememory cell b comes high by writing. This state corresponds to thestorage data “0”. Furth r, when a positive voltage is applied to theselected bit line BL, electrons are not inject d into th floating gateof the select d memory cell. For this reason, the threshold voltage ofthe memory cell does not change after the writing and the cell held inthe erasure state as it is. This state corresponds to the storage data“1”.

[0053]FIGS. 5A and 5B are views of the configuration of a NAND typeflash memory and the erase and write operations thereof. FIG. 5A showsthe operation at the time of erasing, and FIG. 5B shows the operation atthe time of writing. In the NAND type flash memory as well, a pluralityof memory cells are arranged in a matrix. However, unlike the NOR typeflash memory, as shown in FIGS. 5A and 5B, in the NAND type flashmemory, a plurality of memory cells are connected in series between thebit line BL and the source line SL.

[0054] As shown in FIG. 5A, at the time of erasing, a positive highvoltage is applied to the substrate. Due to this, the electrons of thefloating gate are drained to the substrate side, so positive chargeswill accumulate in the floating gate equivalently. For this reason, thethreshold voltage of the memory cell is lowered. Note that, as explainedabove, the storage data of the memory cell in the erasur statecorresponds to “1”.

[0055] The erasing of th memory cell explained above is carri d out withrespect to a plurality of memory cells tog th r. Contrary to this, thewriting of a memory cell is carried out with respect to an individualmemory cell. When writing, the memory cell connected to both of theselected word line WL and the selected bit line BL is selected andwritten in.

[0056] As shown in FIG. 5B, at the time of writing, the source line SLis held at the ground potential GND, the write voltage V_(PP) is appliedto the selected word line WL, and an intermediate voltage V_(pass) isapplied to the other word lines. At this time, the data to be writteninto th selected memory cell is determined in accordance with th voltageapplied to the selected bit line BL. For example, when voltage of 0V isapplied to the selected bit line BL, the channel region of the selectedmemory cell is held at 0V, so the electrons are injected into thefloating gate from that channel region. For this reason, the thresholdvoltage of the memory cell becomes high by the writing. This statecorresponds to the storage data “0”.

[0057] Further, when a positive voltage is applied to the selected bitline BL, the drain region of the selected memory cell is also held atthe positive voltage, so electrons are not injected into the floatinggate of the selected memory cell. For this reason, the threshold voltageof the memory c ll does not change after the writing and is h ld in theerasure state as it is. This state corr sponds to the storage data “1”.

[0058] As explained above, in both NOR type or NAND type flash memories,the erasure is carried out together. The data held in the memory cellafter the erasing becomes “1”. Namely, the storage data of the memorycell in the erasure state is “1”. The writing in a NOR type or NAND typeflash memory is carried out in units of memory cells. By the writing,either of the data “0” or “1” can be. stored in the memory cell.

[0059] Next, the entire operation of the error correction circuit 150 inthe present embodiment will be explained. FIG. 6 and FIG. 7 are flowcharts of the operations at the time of writing and at the time ofreading of the error correction circuit 150 in the present embodiment.Below, an explanation will be given of the operation of the errorcorrection circuit 150 by referring to these flow charts and the circuitshown in FIG. 2.

[0060] First, an explanation will be given of the operation at the timeof the writing by referring to FIG. 6.

[0061] Step SA1: The erasure data D_(E) held in the erasure dataregister 40 is read and input to the coincidence detection circuit 50together with the input write data D_(in).

[0062] Step SA2: The coincid nc detection circuit 50 compares 512 bytesof the user data in th input write data D_(in) with the erasure dataD_(E) read from the erasure data register 40. As a result of thecomparison, when the write data D_(in) and the erasure data D_(E)coincide, the routine proceeds to step SA3 to select the erasure dataD_(E) without selecting a parity bit computed by the ECC encodingcircuit. Conversely, as a result of the above comparison, when the writedata D_(in) and the erasure data D_(E) do not coincide, the routineproceeds to step SA4, where the write data D_(in) after the errorcorrection encoding is selected.

[0063] Step SA5: The selected data D_(W) is written via the flash memoryinterface 170 into the flash memory 180.

[0064] Note that, in the comparison in the coincidence detection circuit50, all bits of the write data D_(in) and the erasure data D_(E) arecompared. As a result, when all bits coincide, a comparison signalS_(CP) indicating the result of decision of coincidence is output, whileif even 1 bit is different, a comparison signal S_(CP) indicating theresult of decision of noncoincidence is output.

[0065]FIG. 8 shows an example of the write data D_(in) stored in thenonvolatile memory. As illustrated, the write data D_(in) is comprisedby 512 bytes of the user data, 15 bytes of th parity bits, and one byteof the management bits. Th parity bits ar writt n with the r sult of theerror correction encoding of the us r data. Th management bits arewritten with attribute information of the user data, for example, copyright information. Note that the management bits are not errorcorrection encoded.

[0066] At the time of writing, the user data of the write data D_(in)shown in FIG. 8 is input to the error correction circuit 150 in units offor example bytes. The erasure data register 40 of the error correctioncircuit 150 holds for example the erasure data D_(E) in units of bytes.For this reason, the coincidence detection circuit 50 sequentiallycompares the user data D_(in) and the erasure data D_(E) input in unitsof bytes. As a result, when all bytes of the user data coincide with theerasure data D_(E), the result of the error correction encoding is notemployed in the parity bits, but the data the same as the erasure datais set. Then, all bytes of the user data and the parity bits are writteninto the flash memory 180 while keeping the erasure data D_(E). Themanagement bits are written with the write data D_(in).

[0067] Conversely, as a result of the detection in the coincidencedetection circuit, when data not coinciding with the erasure data D_(E)is detected in the user data, based on th user data, the errorcorrection code generated by the ECC encoding circuit 20 is set in theparity bits. Then, the parity bits and the manag m nt bits in which thus r data and the error correction code are set are written into theflash memory 180.

[0068] Due to the above writing, when the user data is all erasure dataD_(E), the error correction code is not employed, but the data in theform of erasure data as it is written into the flash memory. Conversely,when data not coinciding with the erasure data is included in the userdata, the parity bits and the management bits in which the user data andthe error correction code generated in accordance with the user data areset are written into the flash memory 180.

[0069] Next, an explanation will be given of the operation at the timeof reading by referring to FIG. 7.

[0070] Step SB1: Data D_(R) is read from the flash memory 180. Notethat, this read data D_(R) includes the user data, parity data, andmanagement data.

[0071] Step SB2: The read data D_(R) and the erasure data D_(E) acquiredfrom the erasure data register 40 are sent to the coincidence detectioncircuit 50 and compared by the coincidence detection circuit. As aresult of the comparison, when the read data D_(R) and the erasure dataD_(E) coincide, the routine proceeds to step SB3, the decoding for theerror detection and the rror correction is not carried out, and thrasure data D_(E) is selected as it is as th read data.

[0072] On th other hand, as a result of the comparison, when the readdata D_(R) and the erasure data D_(E) do not coincide, the routineproceeds to step SB4, the error detection is carried out with respect tothe read data D_(R). When there is error, the error is corrected basedon the user data and the error correction code set in the parity bits.Then, the selection circuit selects the data after the error correction.

[0073] Step SB5: The data selected by the selection circuit 60 isoutput.

[0074] By the write and read operations explained above, when the 512bytes of user data in the write data D_(in) to be stored in the flashmemory coincide with the erasure data D_(E) in the erasure state of theflash memory, the results of the error correction encoding other thanthe management bits are not employed, the user data and all data of theparity bits are set in the erasure data D_(E) and written into the flashmemory. Then, at the time of reading, when the user data and all data ofthe parity bits coincide with the erasure data D_(E), the results of theerror correction decoding other than the management bits are notemployed, and the erasure data D_(E) is output as the read data.Further, in this cas, the error corr ction decoding is not necessary. Byomitting the error correction d coding with its large processing load,the load of th processing circuit can be r duced and accompanyingeffects such as the reduction of the power consumption can be obtained.

[0075] Summarizing the effects of the invention, as explained above,according to the present invention, there is provided a semiconductormemory device for error correction encoding and decoding theinput/output data, wherein in accordance with the status data when theinput data is in a predetermined state of the nonvolatile memory, forexample, the erasure data in the erasure state, the encoded dataobtained by the encoding processing or the erasure data is stored in thenonvolatile memory as it is and, at the time of reading, in accordancewith the comparison result between the read data and the erasure data,the read data can be output as it is without decoding. Therefore,useless processing in writing and reading can be avoided and erroneousdecision in the error correction can be prevented. Further, using theread data, decoding having a large processing load can be omitted, sothere are the advantages that reduction of the processing load andeconomization of the power consumption can be realized.

[0076] While the invention has b en described with reference to specificembodiments chosen for purpose of illustration, it should be apparentthat num rous modifications could be made thereto by those skilled inthe art without departing from the basic concept and scope of theinvention.

What is claimed is:
 1. A semiconductor m mory device comprising: anencoding means for encoding input data according to a predeterminederror correction encoding system; a comparing means for comparing saidinput data and a predetermined status data; a selecting means forselecting either of said input data or encoded data output from saidencoding means in accordance with a comparison result of said comparingmeans; and a nonvolatile memory for storing data selected by saidselecting means, wherein said nonvolatile memory holds said status datain a predetermined initialization state.
 2. A semiconductor memorydevice as set forth in claim 1, wherein said nonvolatile memory holdssaid status data in an erasure state.
 3. A semiconductor memory deviceas set forth in claim 1, wherein said selecting means selects saidstatus data when said input data coincides with said status data andselects said encoded data output from said encoding means when saidinput data does not coincide with said status data.
 4. A semiconductormemory device comprising: a decoding m ans for decoding data read from anonvolatile memory according to a pr determined error correctiondecoding system; a comparing means for comparing data input to saiddecoding means and predetermined status data; and a selecting means forselecting either of said status data or decoded data output from saiddecoding means in accordance with a comparison result of said comparingmeans, wherein said nonvolatile memory holds said status data in apredetermined initialization state.
 5. A semiconductor memory device asset forth in claim 3, wherein said selecting means selects said statusdata when said read data coincides with said status data and selectssaid decoded data when said read data does not coincide with said statusdata.
 6. A semiconductor memory device for error correctionencoding/decoding input/output data, comprising: an encoding means forencoding input data according to a predetermined error correctionencoding system; a comparing means for comparing said input data andpredetermined status data; a first s lecting means for selecting eitherof said input data or ncod d data output from said encoding means inaccordance with a comparison result of said comparing means; anonvolatile memory for storing data selected by said selecting means; adecoding means for decoding data read from said nonvolatile memoryaccording to a predetermined error correction decoding system; acomparing means for comparing the decoded data output by said decodingmeans and said status data; and a second selecting means for selectingeither of said status data or said decoded data in accordance with thecomparison result of said comparing means, wherein said nonvolatilememory holds said status data in a predetermined initialization state.7. A semiconductor memory device as set forth in claim 6, wherein saidnonvolatile memory holds said status data in an erasure state.